Contents
1. Introduction 15
1.1. Computer’s History 15
1.2. Basic Concepts 18
1.3. HCS08’s History 24
1.4. Controller Continuum 25
1.5. Adoption of the C Language 26
1.6. Development Hardware 27
1.7. Standard Conventions 29
2. The HCS08 Architecture 33
2.1. HCS08 Programmer’s Model 34
2.1.1. Accumulator “A” 34
2.1.2. Program Counter “PC” 35
2.1.3. Index Register “H:X” 35
2.1.4. Stack Pointer “SP” 36
2.1.5. Condition Code Register (CCR) 38
2.1.6. Addressing Modes and Instruction Set 40
2.1.6.1. Addressing Modes 40
2.1.6.2. Data Transfer Instructions 42
2.1.6.3. Arithmetic Instructions 44
2.1.6.4. Logic Instructions 46
2.1.6.5. Compare and Test Instructions 47
2.1.6.6. Test and Change-of-flow Instructions 47
2.1.6.7. Internal-Control Instructions 50
2.1.6.8. Instruction Timing 50
2.1.7. Interrupts 51
2.1.7.1. Interrupt Latency 59
2.1.8. Memory Maps 59
2.1.9. Debug Module 61
2.1.9.1. BKGD/MS Pin 61
2.1.9.2. Background Debug Controller (BDC) 62
2.1.9.3. On-Chip Debug Module (DBG) 62
2.2. Flexis Programmer’s Model 64
2.3. Nomenclature 66
2.4. Available Models 67
2.5. Pinouts 70
3. The Codewarrior IDE 75
3.1. IDE 75
3.2. Creating a New Project 76
3.2.1. Creating a New C Project 80
3.2.2. Linker Configuration File 84
3.2.3. The MAP file 86
3.3. Simulating and Debugging the Project 87
3.4. Simulation 88
3.4.1. Source Window 90
3.4.2. Register Window 91
3.4.3. Memory Window 92
3.4.4. Data Windows 93
3.4.5. Visualization Tool 94
3.5. Basic Debugging 95
3.6. Advanced Debugging Topics 97
3.6.1. Periodical Refresh of Data Windows 97
3.6.2. Conditional Breakpoints: 98
3.6.2.1. Halting Execution on a Write Operation on a Variable 99
3.6.2.2. Halting Execution When a Variable Reaches a Specific Value 100
3.6.2.3. Halting Execution on Breakpoints Combination 101
3.6.3. Profiling 102
3.6.4. Code Coverage 103
3.6.5. Watchpoints 104
4. The C Programming Language 107
4.1. C Language Review 107
4.1.1. Commands and Reserved Keywords 107
4.1.2. The Program Structure 107
4.1.3. Data Types 109
4.1.3.1. Variable Declaration 110
4.1.3.2. Variable Initialization 111
4.1.3.3. Modifiers 111
4.1.4. C Operators and Expressions 112
4.1.5. Complex Types 115
4.1.5.1. Enumerations 115
4.1.5.2. Pointers 116
4.1.5.3. Arrays 118
4.1.5.4. Structures 119
4.1.5.5. Unions 120
4.1.5.6. Type Definitions 121
4.1.6. Statements 122
4.1.6.1. If 122
4.1.6.2. Switch 122
4.1.6.3. While 123
4.1.6.4. Do-while 124
4.1.6.5. For 124
4.1.7. Functions 125
4.2. Compiler Characteristics 126
4.2.1. Language Extensions 126
4.2.2. Compiler Options 130
4.2.3. Memory Models 130
4.2.4. Supported Data Types 131
4.2.4.1. Bit Fields Allocation 131
4.2.5. Calling and Returning Conventions 133
4.2.6. CPU-Flags Access Functions 133
4.3. Embedding Assembly Into C Code 134
4.4. Optimizing C Code 135
4.4.1. Compiler Options 135
4.4.2. Variables 136
5. System Modules 137
5.1. Reset 137
5.1.1. The Reset Pin 138
5.1.2. Software Reset 139
5.1.3. SRS Register 140
5.2. Low-Voltage Detection (LVD) 141
5.2.1. Warning Event 142
5.2.2. Detection Event 143
5.2.3. LVD Module on RC, RD, RE and RG Devices 143
5.2.4. Operation in Stop Modes 144
5.2.5. LVD Registers 144
5.2.5.1. SPMSC1 Register 144
5.2.5.2. SPMSC2 Register 145
5.2.5.3. SPMSC3 Register 146
5.3. Watchdog (COP) 146
5.3.1. Enhanced Watchdog 148
5.4. Device ID 149
5.4.1. Identification Registers 149
5.4.1.1. SDIDH Register 149
5.4.1.2. SDIDL Register 149
5.5. System Option Registers 150
5.5.1. SOPT/SOPT1 Register 150
5.5.2. SOPT2 Register 151
6. Input/Output Ports 153
6.1. I/O Operations 154
6.1.1. Software-controlled 154
6.1.1.1. Output Mode 154
6.1.1.2. Input Mode 157
6.1.2. Peripheral-controlled 159
6.1.3. Ganged Outputs 160
6.1.4. I/O Registers 161
6.1.4.1. PTxD Register 161
6.1.4.2. PTxDD Register 161
6.1.4.3. PTxPE Register 161
6.1.4.4. PTxSE Register 162
6.1.4.5. PTxDS Register 162
6.1.4.6. PTxSET Register 162
6.1.4.7. PTxCLR Register 162
6.1.4.8. PTxTOG Register 163
6.1.4.9. GNGC Register 163
6.2. Interrupts 164
6.2.1. IRQ 164
6.2.1.1. IRQSC Register 166
6.2.2. Keyboard Interrupts (KBI) 167
6.2.2.1. KBI Module Connections 168
6.2.2.2. KBI Module Versions 170
6.2.2.3. KBIxSC Register 170
6.2.2.4. KBIxPE Register 171
6.2.2.5. KBIxES Register 171
6.3. Interfacing to External Signals and Loads 172
6.3.1. Reading External Signals 172
6.3.2. Driving External Loads 173
7. Clocking System 177
7.1. Oscillator 177
7.2. ICS 178
7.2.1. ICS Operating Modes 179
7.2.2. Internal Reference Modes 180
7.2.3. External Reference Modes 183
7.2.4. ICS Version 3 185
7.2.5. ICS Module Versions 187
7.2.6. ICS Registers 187
7.2.6.1. ICSC1 Register 187
7.2.6.2. ICSC2 Register 188
7.2.6.3. ICSSC Register 189
7.2.6.4. ICSTRM Register 190
7.3. ICG 190
7.3.1. Internal References 192
7.3.2. External References 193
7.3.3. ICG Events 194
7.3.4. ICG External Connections 195
7.3.5. ICG Module Versions 195
7.3.6. ICG Registers 195
7.3.6.1. ICGC1 Register 196
7.3.6.2. ICGC2 Register 197
7.3.6.3. ICGS2 Register 197
7.3.6.4. ICGS1 Register 198
7.3.6.5. ICGFLTU and ICGFLTL Register 198
7.3.6.6. ICGTRM Register 199
7.3.7. ICG Examples 199
8. Low Power Modes 203
8.1. Wait Mode 204
8.2. Stop Modes 204
8.2.1. Stop3 Mode 205
8.2.2. Stop2 Mode 207
8.2.3. Stop1 Mode 210
8.3. Low Power Modes on Flexis Devices 212
8.3.1. Low Power Run Mode 212
8.3.2. Low Power Wait Mode 214
8.3.3. Stop Modes 214
8.4. Low Power Control Registers 214
8.4.1. SPMSC2 Register 215
8.5. Clock Gating 216
8.5.1. Clock Gating Registers 216
8.5.1.1. SCGC1 Register 216
8.5.1.2. SCGC2 Register 217
8.6. Some Words on Low Power Techniques 217
9. Timing Peripherals 219
9.1. RTI 220
9.1.1. RTI Registers 224
9.1.1.1. SRTISC Register 225
9.1.2. A Real-Time Clock with the RTI Module 226
9.2. RTC 227
9.2.1. RTC Registers 228
9.2.1.1. RTCSC Register 228
9.2.1.2. RTCCNT Register 229
9.2.1.3. RTCMOD Register 229
9.2.2. Clock Example with the RTC 229
9.3. MTIM 230
9.3.1. MTIM External Connections 231
9.3.2. MTIM Registers 231
9.3.2.1. MTIMCNT Register 231
9.3.2.2. MTIMSC Register 232
9.3.2.3. MTIMCLK Register 232
9.3.2.4. MTIMMOD Register 233
9.3.3. Periodic Interrupts with MTIM 233
9.4. TPM 236
9.4.1. Timer Structure 236
9.4.1.1. External Clock Input 238
9.4.2. Capture/Compare/PWM Channels 238
9.4.2.1. Capture Mode 239
9.4.2.2. Compare Mode 241
9.4.2.3. PWM Mode 244
9.4.3. Coherency Mechanism 249
9.4.4. TPM External Connections 250
9.4.5. TPM Module Versions 251
9.4.6. TPM Registers 251
9.4.6.1. TPMSC Register 252
9.4.6.2. TPMCNTH and TPMCNTL Registers 252
9.4.6.3. TPMMODH and TPMMODL Registers 253
9.4.6.4. TPMCxSC 253
9.4.6.5. TPMCxVH and TPMCxVL Registers 254
9.4.7. PWM Led Dimmer 254
9.4.8. Sound Generation 256
9.4.9. Bit-banged UART Implementation 258
10. Analog Peripherals 263
10.1. Analog Comparator (ACMP) 263
10.1.1. ACMP External Connections and Availability 264
10.1.2. ACMP Module Versions 265
10.1.3. ACMP Registers 265
10.1.3.1. ACMPSC Register 265
10.1.4. ACMP Examples 266
10.2. ADC 269
10.2.1. ADC Clocking Circuitry 271
10.2.2. Initiating/Aborting Conversions 272
10.2.3. Input Channel Selection 272
10.2.4. ADC External Connections 273
10.2.5. ADC Registers 274
10.2.5.1. ADCSC1 Register 274
10.2.5.2. ADCSC2 Register 275
10.2.5.3. ADCCFG Register 275
10.2.5.4. ADCR Registers (ADCRH and ADCRL) 276
10.2.5.5. ADCCV Registers (ADCCVH and ADCCVL) 276
10.2.5.6. APCTL1, APCTL2 and APCTL3 Registers 277
10.2.6. ADC Examples 277
11. Communication Peripherals 283
11.1. SPI 283
11.1.1. SPI Transfers 285
11.1.2. Slave Selection Pin 286
11.1.3. Single Wire Data Mode 286
11.1.4. SPI External Connections 286
11.1.5. SPI Registers 287
11.1.5.1. SPIC1 Register 287
11.1.5.2. SPIC2 Register 288
11.1.5.3. SPIS Register 288
11.1.5.4. SPID Register 289
11.1.5.5. SPIBR Register 289
11.1.6. SPI Examples 289
11.2. I2C Interface 293
11.2.1. I2C Basics 293
11.2.2. I2C Interface Basics 295
11.2.3. Master Mode Operation 296
11.2.4. Slave Mode Operation 297
11.2.5. I2C Bus Arbitration Loss 298
11.2.6. I2C External Connections 298
11.2.7. I2C Module Versions 299
11.2.8. I2C Registers 299
11.2.8.1. IICC Register 299
11.2.8.2. IICS Register 300
11.2.8.3. IICA Register 300
11.2.8.4. IICF Register 301
11.2.8.5. IICD Register 302
11.2.8.6. IICC2 Register 302
11.2.9. Interfacing to an External I2C EEPROM 302
11.3. SCI 308
11.3.1. SCI Transmitter 308
11.3.2. SCI Receiver 311
11.3.2.1. Address Detection 314
11.3.3. Baud Rate Generator 315
11.3.4. Single Wire Operation 317
11.3.5. SCI Interrupts 317
11.3.6. SCI External Connections 318
11.3.7. SCI Module Versions 318
11.3.8. SCI Registers 318
11.3.8.1. SCIC1 Register 319
11.3.8.2. SCIC2 Register 320
11.3.8.3. SCIC3 Register 321
11.3.8.4. SCIS1 Register 322
11.3.8.5. SCIS2 Register 323
11.3.8.6. SCID Register 324
11.3.8.7. SCIBD Registers 324
11.3.9. A Circular Buffer 325
12. FLASH Memory Controller 329
12.1. The FLASH Controller 329
12.1.1. FLASH Controller Commands 330
12.1.1.1. Blank Check 330
12.1.1.2. Single-Byte Program 330
12.1.1.3. Multiple-Byte Program 331
12.1.1.4. Sector Erase 332
12.1.1.5. Mass Erase 333
12.1.2. FLASH Controller Registers 333
12.1.2.1. FCDIV Register 333
12.1.2.2. FSTAT Register 334
12.1.2.3. FCMD Register 334
12.2. FLASH Write Protection 335
12.2.1. Write Protection on AC, AW, JM, LC, QD, QG, SG and SH Devices 335
12.2.2. Write Protection on GB, GT and Rx Devices 336
12.2.3. Write Protection on QE Devices 336
12.3. FLASH Security 337
12.3.1.1. FOPT and NVOPT Registers 338
12.3.2. Storing Non-volatile Data into the FLASH Memory 339
13. Project Examples 345
13.1. Application Design Checklist 345
13.1.1. Hardware 345
13.1.2. Software 345
13.2. Controlling an Alphanumeric LCD Module 346
13.3. RC and Robots Interfacing 360
13.3.1. Understanding Small Servos 360
13.3.2. Generating PPM Signals 360
13.3.3. Reading PPM Signals 365
13.3.4. A Simple DC Motor Speed Controller 367
13.4. I2C ADC and I/O Expander 371
13.5. Playing Music 377
13.6. Experiments with Accelerometers 383
13.6.1. A Simple Tilt Indicator 384
13.6.2. Music-Shake 386
HCS08 Instruction Set 393
ASCII Table 399
Index 401
References 409
Registered Trademarks 411